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pg-dso-28-24 enhanced power hex-half-bridge / double six-driv er tle 6208-6 g data sheet 1 2007-09-12 spt 4 1overview 1.1 features ? six high-side and six low-side-drivers ? free configurable as switch, halfbridge or h-bridge ? optimized for dc motor management applications ? 0.6 a continuous (1 a peak) current per switch ? r ds on ; typ. 0.8 ? , @ 25 c per switch ? outputs fully short circuit protected with diagnosis ? overtemperature-protection with hysteresis and diagnosis ? temperature prewarning ? standard spi-interface ? very low current consumption (typ. 10 a, @ 25 c) in stand-by (inhibit) mode ? over- and undervoltage-lockout ? cmos/ttl compatible inputs with hysteresis ? internal clamp diodes ? enhanced power p-dso-package ? green product (rohs compliant) ? aec qualified functional description the tle 6208-6 g is a fully protected hex - h alf- b ridge- d river designed specifically for automotive and industrial motion control applications. the part is based on infineons smart power technology spt ? which allows bipolar and cmos control circuitry in accordance with dmos power devices existing on the same monolithic circuitry. the six low and high side drivers are freely config urable and can be controlled separately. therefore all kind of loads can be combined . in motion control up to 5 actuators (dc- motors) can be connected to the 6 halfbridge- outputs (cascade conf iguration). operation modes forward (cw), reverse (ccw), brake and high impedance are controlled from a standard spi-interface. the possibility to cont rol the outputs via software from a central logic, allows limiting the power dissipati on. so the standard pg-dso-28-24-package meets the application requirements and saves pcb-board-space and cost. furthermore the build-in features like over- and undervoltage-lockout, over- temperature-protection and t he very low quiescent current in stand-by mode opens a wide range of automotive- an d industrial-applications. type package tle 6208-6 g pg-dso-28-24
tle 6208-6 g data sheet 2 2007-09-12 1.2 pin configuration (top view) figure 1 pg-dso-28-24
tle 6208-6 g data sheet 3 2007-09-12 1.3 pin definitions and functions pin no. symbol function 1outl5 low-side-output 5 ; power-mos open drain with internal reverse diode; no internal clamp diode or active zenering; short circuit protected and open load controlled. 2outh5 high-side-output 5 ; power-mos open source with internal reverse diode; no internal clamp diode or active zenering; short circuit protected and open load controlled. 3outh4 high-side-output 4 ; see pin2. 4outl4 low-side-output 4 ; see pin1. 5 v s power supply ; external connection to pin 10 necessary; needs a blocking capacitor as close as possible to gnd value: 22 f electrolytic in parallel to 220 nf ceramic. 6, 7, 8, 9 gnd ground; reference potential; intern al connection to pin 20, 21, 22 and 23; cooling tab; to reduce thermal re sistance; place cooling areas on pcb close to this pins. 10 v s power supply ; see pin 5. 11 outl3 low-side-output 3 ; see pin1. 12 outh3 high-side-output 3 ; see pin2. 13 outh2 high-side-output 2 ; see pin2. 14 outl2 low-side-output 2 ; see pin1. 15 outh1 high-side-output 1 ; see pin2. 16 outl1 low-side-output 1 ; see pin1. 17 inh inhibit input; has an internal pull down; device is switched in standby condition by pulling the inh terminal low. 18 do serial-data-output; this 3-state output transfers diagnosis data to the control device; the outpu t will remain 3-stated unless the device is selected by a low on chip-select-not (csn); see table 2 for diagnosis protocol. 19 v cc logic supply voltage ; needs a blocking capacitor as close as possible to gnd; value: 10 f electrolytic in parallel to 220 nf ceramic.
tle 6208-6 g data sheet 4 2007-09-12 20, 21, 22, 23 gnd ground 24 csn chip-select-not input ; csn is an active low input; serial communication is enabled by pulling the csn terminal low; csn input should only be transitioned when clk is low; csn has an internal active pull up and requires cmos logic level inputs. 25 clk serial clock input ; clocks the shiftr egister; clk has an internal active pull down and requires cmos logic level inputs. 26 di serial data input; receives serial data from the control device; serial data transmitted to di is an 16bit control word with the least significant bit (lsb) being tran sferred first: the input has an active pull down and requires cmos logic level inputs; di will accept data on the falling edge of clk-signal; see table 1 for input data protocol. 27 outl6 low-side-output 6 ; see pin1. 28 outh6 high-side-output 6 ; see pin2. 1.3 pin definitions and functions (cont?d) pin no. symbol function
tle 6208-6 g data sheet 5 2007-09-12 1.4 functional block diagram figure 2 block diagram tle 6208-6 g
tle 6208-6 g data sheet 6 2007-09-12 1.5 circuit description figure 2 shows a block schematic diagram of the module. there are 6 halfbridge drivers on the right-hand side. an hs dr iver and an ls driver are combined to form a halfbridge driver in each case. the drivers communicate via the internal da ta bus with the logic and the other control and monitoring functions: undervoltage (uv) , overvoltage (ov), overtemperature (tsd), charge pump and fault detect. two connection interfaces are provided for supply to the module: all power drivers are connected to the supply voltage v s . these are monitored by overvoltage and undervoltage comparators with hysteresis, so that the correct function can be checked in the application at any time. the logic is supplied by the v cc voltage, typ. with 5 v. the v cc voltage uses an internally generated power-on reset (por) to initialize the module at power-on. the advantage of this system is that inform ation stored in the logic remain s intact in the event of short- term failures in the supply voltage v s . the system can theref ore continue to operate following v s undervoltage, without having to be reprogrammed. the ?undervoltage? information is stored, and can be read out via the interface. the same logically applies for overvoltage. ?interference spikes? on v s are therefore effectively suppressed. the situation is different in t he case of undervoltage on the v cc connection pin. if this occurs, then the internally stored data is de leted, and the output levels are switched to high-impedance status (tristate). the module is initialized by v cc following restart (power-on reset = por). the 16-bit wide programming word or control word (see table 1 ) is read in via the di data input, and this is synchronized with the clock input clk. the status word appears synchronously at the do data output (see table 2 ). the transmission cycle begins wh en the chip is selected wit h the csn input (h to l). if the csn input changes from l to h then the word which has been read in becomes the control word. the do output switches to trista te status at this point, thereby releasing the do bus circuit for other uses. the inh inhibit input can be used to cut off the complete module. this reduces the current consumption to just a few a, and results in the loss of any data stored. the output levels are switched to tr istate status. the module is reinitialized with the internally generated por (power-on reset) at restart. this feature allows the use of this module in battery-operated applications (vehicle body control applications). every driver block from drv 1 to 6 contains a low-side driver and a high-side driver. the output connections have been selected so that each hs driver and ls driver pair can be combined to form a halfbridge by short-circui ting adjacent connections. the full flexibility of the configuration can be achieved by dissecting the halfbridges into ?quarter-bridges?. table 3 shows examples of possible applications.
tle 6208-6 g data sheet 7 2007-09-12 when commutating inductive loads, the dissipated power peak can be significantly reduced by activating the transistor located pa rallel to the internal freewheeling diode. a special, integrated ?timer? for power on/off times ensures there is no crossover current at the halfbridge. figure 3 configuration examples for ?quarter bridges? on the tle 6208-6 g
tle 6208-6 g data sheet 8 2007-09-12 table 1 table 2 input data protocol diagnosis data protocol bit bit 15 ovlo on/off 15 power supply fail 14 underload sd on/off 14 underload 13 overcurrent sd on/off 13 overload 12 hs-switch 6 12 status hs-switch 6 11 ls-switch 6 11 status ls-switch 6 10 hs-switch 5 10 status hs-switch 5 9 ls-switch 5 9 status ls-switch 5 8 hs-switch 4 8 status hs-switch 4 7 ls-switch 4 7 status ls-switch 4 6 hs-switch 3 6 status hs-switch 3 5 ls-switch 3 5 status ls-switch 3 4 hs-switch 2 4 status hs-switch 2 3 ls-switch 2 3 status ls-switch 2 2 hs-switch 1 2 status hs-switch 1 1 ls-switch 1 1 status ls-switch 1 0 status register reset 0 temp. prewarning h= on l= off h = on l = off
tle 6208-6 g data sheet 9 2007-09-12 table 3 fault result table fault diag.-bit result overcurrent (load) 13 only the fa iled output is switched off. function and protection can be deactivated by bit no. 13. short circuit to gnd (high-side-switch) 13 only the failed output is switched off. function and protection can be deactivated by bit no. 13. short circuit to v s (low-side-switch) 13 only the failed output is switched off. function and protection can be deactivated by bit no. 13. temperature warning 0 reacti on of control device needed. temperature shut down (sd) ? all outputs off. openload 14 only the failed output is switched off. function can be deactivated by bit no. 14. underload 14 only the failed output is switched off. function can be deactivated by bit no. 14. undervoltage lockout (uvlo) 15 all outputs off. overvoltage lockout (ovlo) 15 all outputs off. function can be deactivated by bit no. 15. h = failure; l = no failure.
tle 6208-6 g data sheet 10 2007-09-12 2 electrical characteristics note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. 2.1 absolute maximum ratings parameter symbol limit values unit remarks min. max. voltages supply voltage v s ? 0.3 40 v ? supply voltage v s ? 1 ? v t < 0.5 s; i s > ? 2 a logic supply voltage v cc ? 0.3 5.5 v 0 v < v s < 40 v logic input voltages (di, clk, csn, inh) v i ? 0.3 5.5 v 0 v < v s < 40 v 0 v < v cc < 5.5 v logic output voltage (do) v do ? 0.3 v cc v0 v < v s < 40 v 0 v < v cc < 5.5 v currents output current (cont.), if bit13 (ocsd) is set. i out1-6 ? ? a internal limited output current (cont.), if bit13 (ocsd) is deactivated. i out1-6 ? 1.5 1.5 a v ds = 12 v ? 0.7 0.7 a v ds = 20 v ? 0.25 0.25 a v ds = 40 v output current (peak), if bit13 (ocsd) is set. i out1-6 ? ? a internal limited output current (peak), if bit13 (ocsd) is deactivated. t p < 50 ms; t = 1 s; i out1-6 ? 2 2 a v ds = 12 v ? 0.9 0.9 a v ds = 20 v ? 0.3 0.3 a v ds = 40 v temperatures junction temperature t j ? 40 150 c? storage temperature t stg ? 50 150 c?
tle 6208-6 g data sheet 11 2007-09-12 2.2 operating range parameter symbol limit values unit remarks min. max. supply voltage v s v uv off 40 v after v s rising above v uv on supply voltage slew rate d v s / d t ?10v/ s? logic supply voltage v cc 4.75 5.50 v ? supply voltage increasing v s ? 0.3 v uv on v outputs in tristate supply voltage decreasing v s ? 0.3 v uv off v outputs in tristate logic input voltage (di, clk, csn, inh) v i ? 0.3 v cc v? spi clock frequency f clk ?2mhz? junction temperature t j ? 40 150 c? thermal resistances junction pin r thj-pin ? 25 k/w measured to pin 7 junction ambient r thja ?65k/w?
tle 6208-6 g data sheet 12 2007-09-12 2.3 electrical characteristics 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max. current consumption quiescent current i s ?1020 a inh = low; v s = 13.2 v; t j = 25 c quiescent current i s ??40 a inh = low; v s = 13.2 v supply current i s ?2.04.0ma? logic-supply current i cc ?210 a inh = low logic-supply current i cc ? 1.6 3.0 ma spi not active over- and under-voltage lockout uv-switch-on voltage v uv on ?6.57.0v v s increasing uv-switch-off voltage v uv off 5.56.06.6v v s decreasing uv-on/off-hysteresis v uv hy ?0.5?v v uv on ? v uv off ov-switch-off voltage v ov off 34 37 40 v v s increasing ov-switch-on voltage v ov on 28 32 36 v v s decreasing ov-on/off-hysteresis v ov hy ?5.0?v v ov off ? v ov on
tle 6208-6 g data sheet 13 2007-09-12 outputs outh1-6 and outl1-6 static drain-source-on resistance source (high-side) i out = ? 0.5 a r ds on h ?0.91.3 ? 8v < v s < 40 v t j = 25 c ?2.0 ? 8v < v s < 40 v 2.0 ? ? v soff < v s 8v t j = 25 c ?4.0 ? v soff < v s 8v sink (low-side) i out = 0.5 a r ds on l ?0.81.2 ? 8v < v s < 40 v t j = 25 c ?2.0 ? 8v < v s < 40 v 2.0 ? ? v soff < v s 8v t j = 25 c ?4.0 ? v soff < v s 8v note: values of r ds on for v soff < v s 8v are guaranteed by design. leakage current source-output-stage 1 to 6 i qlh ?1 ? ? a v outh1-6 = 0 v t j = 25 c source-output-stage 1 to 6 i qlh ?5 ? ? a v outh1-6 = 0 v sink-output-stage 1 to 6 i qll ??1 a v outl1-6 = v s t j = 25 c sink-output-stage 1 to 6 i qll ??5 a v outl1-6 = v s 2.3 electrical characteristics (cont?d) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j < 150 c; unless otherwise specified parameter symbol limit va lues unit test condition min. typ. max.
tle 6208-6 g data sheet 14 2007-09-12 overcurrent source shutdown threshold i sdu ?2.0 ?1.5 ?1.0 a ? sink shutdown threshold i sdl 1.01.52.0a ? current limit i ocl ? 3.0 5.0 a sink and source shutdown delay time t dsd 10 25 50 s sink and source open circuit detection current i ocd 15 30 50 ma ? delay time t doc 200 350 600 s? delay time from st and-by to data in setup time t set ??100 s? note: setup time is guarnteed by design output delay times; v s = 13.2 v; r load = 25 ? (device not in stand-by for t > 1 ms) source (high-side) on t donh ?7.512 s? source (high-side) off t doffh ?36 s? sink (low-side) on t donl ?6.512 s? sink (low-side) off t doffl ?25 s? dead time h to l t dhl 1.5 ? ? s t donl ? t doffh dead time l to h t dlh 2.5 ? ? s t donh ? t doffl 2.3 electrical characteristics (cont?d) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 6208-6 g data sheet 15 2007-09-12 output switching times; v s = 13.2 v; r load = 25 ? (device not in stand-by for t > 1 ms) source (high-side) rise-time t on h ?48 s? source (high-side) fall-time t off h ?23 s? sink (low-side) fall-time t on l ?13 s? sink (low-side) rise-time t off l ?12 s? clamp diodes forward voltage upper v fu ?0.91.3v i f = 0.5 a lower v fl ?0.91.3v i f = 0.5 a inhibit input h-input voltage threshold v ih ??0.7 v cc ? l-input voltage threshold v il 0.2 ? ? v cc ? hysteresis of input voltage v ihy 50 200 500 mv ? pull down current i i 10 25 50 a v i = 0.2 v cc input capacitance c i ?1015pf0v < v cc < 5.25 v note: capacitances are guaranteed by design 2.3 electrical characteristics (cont?d) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j < 150 c; unless otherwise specified parameter symbol limit va lues unit test condition min. typ. max.
tle 6208-6 g data sheet 16 2007-09-12 spi-interface delay time from st and-by to data in setup time t set ??100 s? logic inputs di, clk and csn h-input voltage threshold v ih ??0.7 v cc ? l-input voltage threshold v il 0.2 ? ? v cc ? hysteresis of input voltage v ihy 50 200 500 mv ? pull up current at pin csn i icsn ?50 ?25 ?10 a v csn = 0.7 v cc pull down current at pin di i idi 10 25 50 a v di = 0.2 v cc pull down current at pin clk i iclk 10 25 50 a v clk = 0.2 v cc input capacitance at pin csn, di or clk c i ? 1015pf0v < v cc < 5.25 v note: capacitances are guaranteed by design logic output do h-output voltage level v doh v cc ? 1.0 v cc ? 0.7 ?v i doh =1 ma l-output voltage level v dol ? 0.2 0.4 v i dol = ? 1.6 ma tri-state leakage current i dolk ? 10 ? 10 a v csn = v cc 0v < v do < v cc tri-state input capacitance c do ? 1015pf v csn = v cc 0v < v cc < 5.25 v note: capacitances are guaranteed by design 2.3 electrical characteristics (cont?d) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 6208-6 g data sheet 17 2007-09-12 data input timing clock period t pclk 500 ? ?ns? clock high time t clkh 250 ? ?ns? clock low time t clkl 250 ? ?ns? clock low before csn low t bef 250 ? ?ns? csn setup time t lead 250 ? ?ns? csn high time t csnh 12 ? ? s? clk setup time t lag 250 ? ?ns? clock low after csn high t beh 250 ? ?ns? di setup time t disu 40 ? ?ns? di hold time t diho 40 ? ?ns? input signal rise time at pin di, clk and csn t rin ? ?200ns? input signal fall time at pin di, clk and csn t fin ? ?200ns? data output timing do rise time t rdo ?50100ns c l = 100 pf do fall time t fdo ?50100ns c l = 100 pf do enable time t endo ? ? 250 ns low impedance do disable time t disdo ? ? 250 ns high impedance do valid time t vado ? 100 250 ns v do < 0.2 v cc ; v do > 0.7 v cc ; c l = 100 pf note: spi timing ia guaranteed by design. csn high time: this is the minimum time the user must wait between spi commands. 2.3 electrical characteristics (cont?d) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j < 150 c; unless otherwise specified parameter symbol limit va lues unit test condition min. typ. max.
tle 6208-6 g data sheet 18 2007-09-12 thermal prewarning and shutdown thermal prewarning junction temperature t jpw 120 145 170 c? temperature prewarning hysteresis ? t ?30 ?k? thermal shutdown junction temperature t jsd 150 175 200 c? thermal switch-on junction temperature t jso 120 ? 170 c? temperature shutdown hysteresis ? t ?30 ?k? ratio of sd to pw temperature t jsd / t jpw 1.05 1.20 ? ? ? note: temperatures are guaranteed by design 2.3 electrical characteristics (cont?d) 8v< v s < 40 v; 4.75 v < v cc < 5.25 v; inh = high; all outputs open; ? 40 c< t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 6208-6 g data sheet 19 2007-09-12 3 timing diagrams figure 4 standard data transfer timing figure 5 timing for temperature prewarning only 15 0 123 4 5678 9 10 11 12 13 14 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 di clk csn 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 do csn high to low & rising edge of clk: do is enabled. status information is transfered to output shift register csn low to high: data from shift-register is transfered to output power switches previous status actual data di: data will be accepted on the falling edge of clk-signal do: state will change on the rising edge of clk-signal __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ time 1 0 0 01 1 ++ new data actual status eg. hs1 actual data old data di clk csn 0 do csn high to low & clk stays low: status information of data bit 0 ( temperature prewarning ) is transfered to do di: data is not accepted do: status information of data bit 0 ( temperature prewarning ) will stay as long as csn is low time _
tle 6208-6 g data sheet 20 2007-09-12 figure 6 spi-input timing figure 7 turn off/on time t don csn 70 % 20 % 50 % t doff t rin t fin case 2 i out 90 % 10 % off state t on on state case 1 i out 50 % 90% 10 % 50 % t off off state on state t csnh
tle 6208-6 g data sheet 21 2007-09-12 figure 8 do valid data delay time and valid time figure 9 do enable and disable time t vado do clk 0.7 v cc 0.2 v cc 0.7 v cc 0.2 v cc 50 % t rdo ( low to high ) t rin t fin do 0.7 v cc 0.2 v cc ( high to low ) t fdo csn 0.7 v cc 0.2 v cc 50 % t fin t rin do t endo 50 % t disdo do t endo 50 % t disdo 10 k ? pullup to v cc 10 k ? pulldown to gnd
tle 6208-6 g data sheet 22 2007-09-12 4application figure 10 application circuit
tle 6208-6 g data sheet 23 2007-09-12 5 package outlines figure 11 pg-dso-28-24 (plastic dual small outline) green product (rohs compliant) to meet the world-wide customer requireme nts for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). gps05123 you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm smd = surface mounted device
tle 6208-6 g data sheet 24 2007-09-12 revision history version date changes rev. 1.1 2007-09-12 rohs-compliant version of the tle 6208-6 g ? all pages: infineon logo updated ? page 1: ?added aec qualified? and ?roh s? logo, ?green product (rohs compliant)? and ?aec qualified? statement added to feature list, package name changed to rohs compliant versions, package picture updated, ordering code removed ? page 23: package name changed to rohs compliant versions, ?green product? description added ? page 24-25: added revision history and legal disclaimer
tle 6208-6 g data sheet 25 2007-09-12 edition 2007-09-12 published by infineon technologies ag 81726 munich, germany ? 9/14/07 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints gi ven herein, any typical values stated herein and/or any information regarding the application of the device, in fineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the neares t infineon technologies office. infineon technologies components may be used in life-supp ort devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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